The present invention relates to a semiconductor device and, more particularly, to the construction of a vertical field effect transistor which is used as a device for high-speed switching operation and a power device.
The trend in power sources used in CPUs (Central Processing Units) of computers and the like is reduction of an output voltage level. In this connection, power sources by synchronous rectifier techniques have been frequently used. As a semiconductor device applied to a power source by synchronous rectifier techniques, there is a MOSFET (a Metal Oxide Semiconductor Field Effect Transistor), for example. And in this MOSFET, it is required that switching losses and conducting losses of a switching component on the high-voltage side be reduced. As prior art which involves providing a gate electrode via a gate insulating film within a trench up to a semiconductor substrate of the first conduction type after the passage of a base (body) region, there are vertical MOSFETs disclosed in the Japanese Patent Laid-Open No. 5-335582 and the Japanese Patent Laid-Open No. 7-326755. Also, as prior art which involves providing silicide on the top surface of an upper end portion of a gate electrode, there is a MOSFET disclosed in the Japanese Patent Laid-Open No. 2002-368220.
FIG. 17 shows the sectional construction of a conventional MOSFET and a detailed construction of the conventional MOSFET will be described by using this figure. For a simplified description, an n-channel type MOSFET is taken as an example. By reversing p to n, the same description applies to a p-channel type MOSFET. An n−-type semiconductor layer 2 is formed on an n+-type semiconductor substrate 1 by epitaxial growth. A p-type base region 3 is formed on this n−-type semiconductor layer 2, and a trench 4 is formed so as to penetrate the p-type base region 3. A gate insulating film 5 is present on the surface of this trench 4, and via this gate insulating film 5 polycrystalline silicon is buried as a gate 6. Adjacent to this trench 4, an n+-type source 7 and a p+-type contact region 8 which comes into contact with a p-type base region 3 are provided. A source electrode 9 is formed via top metals 9a, 9b each of which comes into contact with both of the source region 7 and the body region (contact region 8). A drain electrode 10 is formed on the back side of the n+-type semiconductor substrate 1.
It is generally known that reducing the feedback capacitance Cgd between the gate and the drain of the gate insulating film 5 shown in FIG. 17 is important for reducing switching losses. In order to reduce the feedback capacitance Cgd between the gate and the drain, it is conceivable to shorten the length of a portion protruding from the p-type base region 3 or narrow the width (thickness) of the trench. Also, because it is effective to shorten the channel length in reducing the on-resistance of a MOSFET, it is conceivable to shorten the length d in FIG. 17 which corresponds to the depth of the trench 4.
When switching losses and conducting losses are to be reduced by use of the above-described construction in a semiconductor device such as a vertical field-effect transistor, the sectional area of a gate electrode and polycrystalline silicon in a direction orthogonal to the direction in which a drain current flows decreases. Gate resistance increases when such a construction is adopted. Therefore, there has been known a construction in which a lower portion of the gate electrode 6 present within the trench 4 is constructed to be slender and the upper portion is widened via a stepped part and a silicide region 11, which is formed as a metal film formed from a metal or a metal oxide, is added to the upper part of the gate electrode 6. Gate resistance can be decreased by increasing the area of the silicide region 11 as a metal film.
In the conventional construction, the length Lf of the portion which is expanded wider than the lower portion of the gate electrode 6 is increased, whereby the area of the silicidized region 11 is increased and gate resistance can be reduced. On the other hand, however, the gate-source capacitance Cgs in the gate insulating film 5 between the source region 7 and the expanded portion opposite to this source region 7 also increases and this leads to an increase in the input capacitance of the MOSFET. Such an increase in the input capacitance results in an increase in drive losses in the MOSFET and becomes the cause of worsening of the efficiency of a power supply. That is, a decrease in gate resistance and a decrease in the input capacitance are in antimonic relation, and a tradeoff relation arises in such a manner that an increase in the input capacitance is induced if only a reduction of gate resistance is sought after, whereas gate resistance increases if the input capacitance is to be reduced.
As is apparent from the above description, if the area of the silicidized region is increased by increasing the length of the expanded portion of the conventional construction, the gate-source capacitance Cgs in the gate insulating film 5 between the expanded portion and the source region 7 increases and this leads to an increase in the input capacitance of the MOSFET. Such an increase in the input capacitance results in an increase in drive losses in the MOSFET and becomes the cause of worsening of the efficiency of a power supply.
It is desired to provide a semiconductor device which reduces gate resistance by ensuring a sufficient area of a silicide region and can prevent an increase in drive losses by preventing an increase in the input capacitance.